1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having an improved arrangement of power source lines and special signal lines such as clock signal lines.
2. Description of the Prior Art
FIG. 1 shows an arrangement of power source lines in a semiconductor integrated circuit device according to a prior art. Although actual power source lines include power supply lines and ground lines, the following explanation collectively expresses them as power source lines for the sake of simplicity.
The device includes a macro block 101 to provide at least one function and cell strings 102 that form a cell string area 103. An I/O cell area 104 is formed at the periphery of the device. The macro block 101 includes a CPU and memories such as RAMs and ROMs. Each of the cell strings 102 consists of a sequence of logic gate cells. The I/O cell area 104 includes I/O cells 105 that transmit and receive signals to and from the outside of the device.
The macro block 101 and cell strings 102 receive power from the I/O cells 105. Power source lines 110A extend from corresponding I/O cells 105 directly to the cell strings 102. These lines 110A are connected to power source lines 110B, which are formed in the cell strings 102 and are connected to power source lines 110C.
Power source lines 110D extend from corresponding I/O cells 105 to a power source ring of the macro block 101. The power source ring is connected to the power source lines 110C, which are connected to the cell strings 102.
Power source lines 110E extend from corresponding I/O cells 105 to the cell strings 102. These lines 110E are connected to power source lines 110F, which are formed in the cell strings 102 and are connected to inter-cell power source lines 110G.
FIG. 2 shows the details of the power source ring formed around the macro block 101.
Due to the limitation of an automatic wiring technique employing, for example, CAD, macro blocks usually have a ring-shaped power source line. In FIG. 2, the macro block 101 is surrounded with the power source ring 101A consisting of a ground ring 101a and a power supply ring 101b.
The power source lines 110D extending from the corresponding I/O cells 105 are connected to the power source ring 101A, which is connected to the power source lines 110C that are connected to the cell strings 102.
FIG. 3 shows a clock signal line arranged in a semiconductor integrated circuit device according to another prior art. The device has a macro block 201, cell strings 202, 203, and 204, and I/O cells 205. These elements correspond to those of FIG. 1. The I/O cells 205 include an internal clock generator 205a made of, for example, a PLL circuit for generating an internal clock signal, which is supplied to the cell strings 202 to 204.
The macro block 201 is arranged between the internal clock generator 205a and a cell string area where the cell strings 202 to 204 are formed. As a result, the clock signal line from the generator 205a must detour around the macro block 201 to the cell string area.
The internal clock signal generated by the generator 205a is passed through the clock signal line 206A to clock buffers 202a to 204a, which drive the clock signal and supply the same to the respective cell strings 202 to 204. The problems of these prior arts will be explained.
(1) In the prior art of FIG. 1, power passing through the power source lines 110A is directly supplied to the cell strings 102 for the full width of the lines 110A. On the other hand, power passing through the power source lines 110D is indirectly supplied to the cell strings 102 through the power source ring 101A due to the presence of the macro block 101. The reason of using the ring 101A instead of making a detour around the macro block 101 is to reduce the area of the device.
The width of the power source ring 101A determines the quantity of power supplied to the cell strings 102 through the power source lines 110C, which connect the ring 101A to the cell strings 102. If the total width "P1+P2+P3" (FIG. 2) of the lines 110C is greater than the width P0 of the ring 101A, the quantity of power supplied to the cell strings 102 will be short. Namely, the width of the ring 101A must be greater than the total width of the lines 110C, to prevent a power supply shortage.
(2) In the prior art of FIG. 3, the clock signal line 206A extending from the internal clock generator 205a detours around the macro block 201. This arrangement increases the area of the device, elongates the line 206A, and worsens a clock skew.